./chc-comp-wrapper.sh ../../../chc-comp24-benchmarks/LIA/chc-comp24-LIA-063.smt2 .


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This is Ultimate 0.3.0-dev-42d8767-m
[2025-04-28 21:21:48,317 INFO  L188        SettingsManager]: Resetting all preferences to default values...
[2025-04-28 21:21:48,431 INFO  L114        SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_72851e35-70e5-489e-8868-e4e2bb8e44d1/chc-comp25-scripts/participants/UltimateUnihorn/./chccomp-Unihorn_Default.epf
[2025-04-28 21:21:48,437 WARN  L101        SettingsManager]: Preference file contains the following unknown settings:
[2025-04-28 21:21:48,438 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2025-04-28 21:21:48,487 INFO  L130        SettingsManager]: Preferences different from defaults after loading the file:
[2025-04-28 21:21:48,487 INFO  L151        SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2025-04-28 21:21:48,488 INFO  L153        SettingsManager]:  * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2025-04-28 21:21:48,489 INFO  L151        SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults:
[2025-04-28 21:21:48,490 INFO  L153        SettingsManager]:  * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS
[2025-04-28 21:21:48,491 INFO  L151        SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2025-04-28 21:21:48,491 INFO  L153        SettingsManager]:  * Create parallel compositions if possible=false
[2025-04-28 21:21:48,491 INFO  L153        SettingsManager]:  * Use SBE=true
[2025-04-28 21:21:48,491 INFO  L151        SettingsManager]: Preferences of ChcToBoogie differ from their defaults:
[2025-04-28 21:21:48,491 INFO  L153        SettingsManager]:  * Use one large procedure with gotos to replace tail recursive calls=false
[2025-04-28 21:21:48,492 INFO  L151        SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2025-04-28 21:21:48,492 INFO  L153        SettingsManager]:  * Size of a code block=SequenceOfStatements
[2025-04-28 21:21:48,492 INFO  L153        SettingsManager]:  * SMT solver=External_DefaultMode
[2025-04-28 21:21:48,492 INFO  L153        SettingsManager]:  * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000
[2025-04-28 21:21:48,492 INFO  L151        SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2025-04-28 21:21:48,492 INFO  L153        SettingsManager]:  * Compute Interpolants along a Counterexample=FPandBP
[2025-04-28 21:21:48,492 INFO  L153        SettingsManager]:  * Trace refinement strategy=CAMEL
[2025-04-28 21:21:48,493 INFO  L153        SettingsManager]:  * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in
[2025-04-28 21:21:48,493 INFO  L153        SettingsManager]:  * Automaton type used in concurrency analysis=PETRI_NET
[2025-04-28 21:21:48,493 INFO  L153        SettingsManager]:  * SMT solver=External_ModelsAndUnsatCoreMode
[2025-04-28 21:21:48,494 INFO  L151        SettingsManager]: Preferences of SmtParser differ from their defaults:
[2025-04-28 21:21:48,494 INFO  L153        SettingsManager]:  * SmtParser Mode=UltimateTreeAutomizer
[2025-04-28 21:21:48,916 INFO  L75    nceAwareModelManager]: Repository-Root is: /tmp
[2025-04-28 21:21:48,932 INFO  L261   ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2025-04-28 21:21:48,935 INFO  L217   ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2025-04-28 21:21:48,940 INFO  L270        PluginConnector]: Initializing SmtParser...
[2025-04-28 21:21:48,940 INFO  L274        PluginConnector]: SmtParser initialized
[2025-04-28 21:21:48,942 INFO  L431   ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_72851e35-70e5-489e-8868-e4e2bb8e44d1/chc-comp25-scripts/participants/UltimateUnihorn/../../../chc-comp24-benchmarks/LIA/chc-comp24-LIA-063.smt2
[2025-04-28 21:21:48,945 INFO  L314              SmtParser]: Parsing .smt2 file as a set of Horn Clauses
[2025-04-28 21:21:48,950 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
unknown
[2025-04-28 21:21:49,278 INFO  L339              SmtParser]: Successfully executed SMT file /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_72851e35-70e5-489e-8868-e4e2bb8e44d1/chc-comp25-scripts/participants/UltimateUnihorn/../../../chc-comp24-benchmarks/LIA/chc-comp24-LIA-063.smt2
[2025-04-28 21:21:49,281 INFO  L299   ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2025-04-28 21:21:49,283 INFO  L133        ToolchainWalker]: Walking toolchain with 4 elements.
[2025-04-28 21:21:49,283 INFO  L112        PluginConnector]: ------------------------ChcToBoogie----------------------------
[2025-04-28 21:21:49,284 INFO  L270        PluginConnector]: Initializing ChcToBoogie...
[2025-04-28 21:21:49,284 INFO  L274        PluginConnector]: ChcToBoogie initialized
[2025-04-28 21:21:49,291 INFO  L184        PluginConnector]: Executing the observer ChcToBoogieObserver from plugin ChcToBoogie for "de.uni_freiburg.informatik.ultimate.source.smtparser OTHER 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,335 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49 Unit
[2025-04-28 21:21:49,336 INFO  L131        PluginConnector]: ------------------------ END ChcToBoogie----------------------------
[2025-04-28 21:21:49,339 INFO  L112        PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2025-04-28 21:21:49,339 INFO  L270        PluginConnector]: Initializing Boogie Preprocessor...
[2025-04-28 21:21:49,339 INFO  L274        PluginConnector]: Boogie Preprocessor initialized
[2025-04-28 21:21:49,354 INFO  L184        PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,354 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,377 INFO  L184        PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,377 INFO  L184        PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,381 INFO  L184        PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,382 INFO  L184        PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,384 INFO  L184        PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,385 INFO  L184        PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,386 INFO  L184        PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,401 INFO  L131        PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2025-04-28 21:21:49,404 INFO  L112        PluginConnector]: ------------------------RCFGBuilder----------------------------
[2025-04-28 21:21:49,404 INFO  L270        PluginConnector]: Initializing RCFGBuilder...
[2025-04-28 21:21:49,404 INFO  L274        PluginConnector]: RCFGBuilder initialized
[2025-04-28 21:21:49,405 INFO  L184        PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (1/1) ...
[2025-04-28 21:21:49,408 INFO  L173          SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000
[2025-04-28 21:21:49,421 INFO  L189       MonitoredProcess]: No working directory specified, using /usr/bin/z3
[2025-04-28 21:21:49,436 INFO  L229       MonitoredProcess]: Starting monitored process 1 with /usr/bin/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null)
[2025-04-28 21:21:49,441 INFO  L327       MonitoredProcess]: [MP /usr/bin/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process
[2025-04-28 21:21:49,455 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure False given in one single declaration
[2025-04-28 21:21:49,456 INFO  L130     BoogieDeclarations]: Found specification of procedure False
[2025-04-28 21:21:49,456 INFO  L138     BoogieDeclarations]: Found implementation of procedure False
[2025-04-28 21:21:49,456 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure ERR given in one single declaration
[2025-04-28 21:21:49,456 INFO  L130     BoogieDeclarations]: Found specification of procedure ERR
[2025-04-28 21:21:49,456 INFO  L138     BoogieDeclarations]: Found implementation of procedure ERR
[2025-04-28 21:21:49,456 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure MAIN given in one single declaration
[2025-04-28 21:21:49,456 INFO  L130     BoogieDeclarations]: Found specification of procedure MAIN
[2025-04-28 21:21:49,456 INFO  L138     BoogieDeclarations]: Found implementation of procedure MAIN
[2025-04-28 21:21:49,457 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure top_step given in one single declaration
[2025-04-28 21:21:49,457 INFO  L130     BoogieDeclarations]: Found specification of procedure top_step
[2025-04-28 21:21:49,457 INFO  L138     BoogieDeclarations]: Found implementation of procedure top_step
[2025-04-28 21:21:49,457 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure sustain_step given in one single declaration
[2025-04-28 21:21:49,457 INFO  L130     BoogieDeclarations]: Found specification of procedure sustain_step
[2025-04-28 21:21:49,457 INFO  L138     BoogieDeclarations]: Found implementation of procedure sustain_step
[2025-04-28 21:21:49,457 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure fedge_step given in one single declaration
[2025-04-28 21:21:49,457 INFO  L130     BoogieDeclarations]: Found specification of procedure fedge_step
[2025-04-28 21:21:49,457 INFO  L138     BoogieDeclarations]: Found implementation of procedure fedge_step
[2025-04-28 21:21:49,457 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure redge_step given in one single declaration
[2025-04-28 21:21:49,458 INFO  L130     BoogieDeclarations]: Found specification of procedure redge_step
[2025-04-28 21:21:49,458 INFO  L138     BoogieDeclarations]: Found implementation of procedure redge_step
[2025-04-28 21:21:49,458 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure top_reset given in one single declaration
[2025-04-28 21:21:49,458 INFO  L130     BoogieDeclarations]: Found specification of procedure top_reset
[2025-04-28 21:21:49,458 INFO  L138     BoogieDeclarations]: Found implementation of procedure top_reset
[2025-04-28 21:21:49,458 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure sustain_reset given in one single declaration
[2025-04-28 21:21:49,458 INFO  L130     BoogieDeclarations]: Found specification of procedure sustain_reset
[2025-04-28 21:21:49,458 INFO  L138     BoogieDeclarations]: Found implementation of procedure sustain_reset
[2025-04-28 21:21:49,458 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure fedge_reset given in one single declaration
[2025-04-28 21:21:49,458 INFO  L130     BoogieDeclarations]: Found specification of procedure fedge_reset
[2025-04-28 21:21:49,458 INFO  L138     BoogieDeclarations]: Found implementation of procedure fedge_reset
[2025-04-28 21:21:49,459 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure redge_reset given in one single declaration
[2025-04-28 21:21:49,459 INFO  L130     BoogieDeclarations]: Found specification of procedure redge_reset
[2025-04-28 21:21:49,459 INFO  L138     BoogieDeclarations]: Found implementation of procedure redge_reset
[2025-04-28 21:21:49,459 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure INIT_STATE given in one single declaration
[2025-04-28 21:21:49,459 INFO  L130     BoogieDeclarations]: Found specification of procedure INIT_STATE
[2025-04-28 21:21:49,459 INFO  L138     BoogieDeclarations]: Found implementation of procedure INIT_STATE
[2025-04-28 21:21:49,459 INFO  L124     BoogieDeclarations]: Specification and implementation of procedure Ultimate.START given in one single declaration
[2025-04-28 21:21:49,459 INFO  L130     BoogieDeclarations]: Found specification of procedure Ultimate.START
[2025-04-28 21:21:49,459 INFO  L138     BoogieDeclarations]: Found implementation of procedure Ultimate.START
[2025-04-28 21:21:49,585 INFO  L234             CfgBuilder]: Building ICFG
[2025-04-28 21:21:49,586 INFO  L260             CfgBuilder]: Building CFG for each procedure with an implementation
[2025-04-28 21:21:49,810 INFO  L?                        ?]: Removed 16 outVars from TransFormulas that were not future-live.
[2025-04-28 21:21:49,810 INFO  L283             CfgBuilder]: Performing block encoding
[2025-04-28 21:21:49,824 INFO  L304             CfgBuilder]: Using library mode
[2025-04-28 21:21:49,825 INFO  L312             CfgBuilder]: Removed 5 assume(true) statements.
[2025-04-28 21:21:49,825 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.04 09:21:49 BoogieIcfgContainer
[2025-04-28 21:21:49,825 INFO  L131        PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2025-04-28 21:21:49,828 INFO  L112        PluginConnector]: ------------------------TraceAbstraction----------------------------
[2025-04-28 21:21:49,828 INFO  L270        PluginConnector]: Initializing TraceAbstraction...
[2025-04-28 21:21:49,833 INFO  L274        PluginConnector]: TraceAbstraction initialized
[2025-04-28 21:21:49,833 INFO  L184        PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.source.smtparser OTHER 28.04 09:21:49" (1/3) ...
[2025-04-28 21:21:49,834 INFO  L204        PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@200e416a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction OTHER 28.04 09:21:49, skipping insertion in model container
[2025-04-28 21:21:49,834 INFO  L184        PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.chctoboogie AST 28.04 09:21:49" (2/3) ...
[2025-04-28 21:21:49,835 INFO  L204        PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@200e416a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.04 09:21:49, skipping insertion in model container
[2025-04-28 21:21:49,835 INFO  L184        PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.04 09:21:49" (3/3) ...
[2025-04-28 21:21:49,836 INFO  L128   eAbstractionObserver]: Analyzing ICFG de.uni_freiburg.informatik.ultimate.plugins.chctoboogie.ChcToBoogieObserver
[2025-04-28 21:21:49,856 INFO  L217   ceAbstractionStarter]: Automizer settings: Hoare:None NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION
[2025-04-28 21:21:49,863 INFO  L151   ceAbstractionStarter]: Applying trace abstraction to ICFG de.uni_freiburg.informatik.ultimate.plugins.chctoboogie.ChcToBoogieObserver that has 13 procedures, 59 locations, 95 edges, 13 initial locations, 0 loop locations, and 1 error locations.
[2025-04-28 21:21:49,917 INFO  L339      AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ========
[2025-04-28 21:21:49,931 INFO  L340      AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=None, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@6fab7493, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms]
[2025-04-28 21:21:49,931 INFO  L341      AbstractCegarLoop]: Starting to check reachability of 1 error locations.
[2025-04-28 21:21:49,936 INFO  L278                IsEmpty]: Start isEmpty. Operand  has 59 states, 22 states have (on average 1.0454545454545454) internal successors, (23), 23 states have internal predecessors, (23), 23 states have call successors, (24), 12 states have call predecessors, (24), 12 states have return successors, (24), 23 states have call predecessors, (24), 23 states have call successors, (24)
[2025-04-28 21:21:49,949 INFO  L284                IsEmpty]: Finished isEmpty. Found accepting run of length 93
[2025-04-28 21:21:49,949 INFO  L210           NwaCegarLoop]: Found error trace
[2025-04-28 21:21:49,950 INFO  L218           NwaCegarLoop]: trace histogram [6, 6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-04-28 21:21:49,951 INFO  L403      AbstractCegarLoop]: === Iteration 1 === Targeting Ultimate.STARTErr0ASSERT_VIOLATIONCHC_SATISFIABILITY === [Ultimate.STARTErr0ASSERT_VIOLATIONCHC_SATISFIABILITY] ===
[2025-04-28 21:21:49,957 INFO  L155       PredicateUnifier]: Initialized classic predicate unifier
[2025-04-28 21:21:49,957 INFO  L85        PathProgramCache]: Analyzing trace with hash -1161333958, now seen corresponding path program 1 times
[2025-04-28 21:21:49,970 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-04-28 21:21:49,971 INFO  L324   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029255633]
[2025-04-28 21:21:49,971 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-04-28 21:21:49,972 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-04-28 21:21:50,070 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes.
[2025-04-28 21:21:50,169 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements.
[2025-04-28 21:21:50,170 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-04-28 21:21:50,170 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-04-28 21:21:51,073 INFO  L134       CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked.
[2025-04-28 21:21:51,073 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-04-28 21:21:51,074 INFO  L324   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029255633]
[2025-04-28 21:21:51,074 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1029255633] provided 1 perfect and 0 imperfect interpolant sequences
[2025-04-28 21:21:51,075 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-04-28 21:21:51,079 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7
[2025-04-28 21:21:51,082 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649347807]
[2025-04-28 21:21:51,082 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-04-28 21:21:51,089 INFO  L562      AbstractCegarLoop]: INTERPOLANT automaton has 7 states
[2025-04-28 21:21:51,090 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-04-28 21:21:51,131 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants.
[2025-04-28 21:21:51,132 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42
[2025-04-28 21:21:51,134 INFO  L87              Difference]: Start difference. First operand  has 59 states, 22 states have (on average 1.0454545454545454) internal successors, (23), 23 states have internal predecessors, (23), 23 states have call successors, (24), 12 states have call predecessors, (24), 12 states have return successors, (24), 23 states have call predecessors, (24), 23 states have call successors, (24) Second operand  has 7 states, 5 states have (on average 4.2) internal successors, (21), 6 states have internal predecessors, (21), 5 states have call successors, (22), 1 states have call predecessors, (22), 5 states have return successors, (22), 6 states have call predecessors, (22), 5 states have call successors, (22)
[2025-04-28 21:21:51,311 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-04-28 21:21:51,311 INFO  L93              Difference]: Finished difference Result 59 states and 71 transitions.
[2025-04-28 21:21:51,314 INFO  L140   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. 
[2025-04-28 21:21:51,316 INFO  L79                 Accepts]: Start accepts. Automaton has  has 7 states, 5 states have (on average 4.2) internal successors, (21), 6 states have internal predecessors, (21), 5 states have call successors, (22), 1 states have call predecessors, (22), 5 states have return successors, (22), 6 states have call predecessors, (22), 5 states have call successors, (22) Word has length 92
[2025-04-28 21:21:51,317 INFO  L85                 Accepts]: Finished accepts. some prefix is accepted.
[2025-04-28 21:21:51,326 INFO  L225             Difference]: With dead ends: 59
[2025-04-28 21:21:51,326 INFO  L226             Difference]: Without dead ends: 59
[2025-04-28 21:21:51,328 INFO  L436           NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56
[2025-04-28 21:21:51,332 INFO  L437           NwaCegarLoop]: 65 mSDtfsCounter, 2 mSDsluCounter, 299 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 364 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time
[2025-04-28 21:21:51,332 INFO  L438           NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 364 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time]
[2025-04-28 21:21:51,387 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 59 states.
[2025-04-28 21:21:51,431 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59.
[2025-04-28 21:21:51,432 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 59 states, 22 states have (on average 1.0) internal successors, (22), 22 states have internal predecessors, (22), 23 states have call successors, (24), 12 states have call predecessors, (24), 13 states have return successors, (25), 24 states have call predecessors, (25), 23 states have call successors, (25)
[2025-04-28 21:21:51,450 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 71 transitions.
[2025-04-28 21:21:51,453 INFO  L79                 Accepts]: Start accepts. Automaton has 59 states and 71 transitions. Word has length 92
[2025-04-28 21:21:51,455 INFO  L85                 Accepts]: Finished accepts. word is rejected.
[2025-04-28 21:21:51,455 INFO  L485      AbstractCegarLoop]: Abstraction has 59 states and 71 transitions.
[2025-04-28 21:21:51,456 INFO  L486      AbstractCegarLoop]: INTERPOLANT automaton has  has 7 states, 5 states have (on average 4.2) internal successors, (21), 6 states have internal predecessors, (21), 5 states have call successors, (22), 1 states have call predecessors, (22), 5 states have return successors, (22), 6 states have call predecessors, (22), 5 states have call successors, (22)
[2025-04-28 21:21:51,456 INFO  L278                IsEmpty]: Start isEmpty. Operand 59 states and 71 transitions.
[2025-04-28 21:21:51,465 INFO  L284                IsEmpty]: Finished isEmpty. Found accepting run of length 136
[2025-04-28 21:21:51,465 INFO  L210           NwaCegarLoop]: Found error trace
[2025-04-28 21:21:51,465 INFO  L218           NwaCegarLoop]: trace histogram [12, 12, 6, 6, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-04-28 21:21:51,466 WARN  L466      AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1
[2025-04-28 21:21:51,466 INFO  L403      AbstractCegarLoop]: === Iteration 2 === Targeting Ultimate.STARTErr0ASSERT_VIOLATIONCHC_SATISFIABILITY === [Ultimate.STARTErr0ASSERT_VIOLATIONCHC_SATISFIABILITY] ===
[2025-04-28 21:21:51,467 INFO  L155       PredicateUnifier]: Initialized classic predicate unifier
[2025-04-28 21:21:51,467 INFO  L85        PathProgramCache]: Analyzing trace with hash 1797910201, now seen corresponding path program 1 times
[2025-04-28 21:21:51,467 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-04-28 21:21:51,467 INFO  L324   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494625788]
[2025-04-28 21:21:51,467 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-04-28 21:21:51,468 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-04-28 21:21:51,545 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 135 statements into 1 equivalence classes.
[2025-04-28 21:21:51,629 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 135 of 135 statements.
[2025-04-28 21:21:51,629 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-04-28 21:21:51,629 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-04-28 21:21:51,630 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-04-28 21:21:51,677 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 135 statements into 1 equivalence classes.
[2025-04-28 21:21:51,719 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 135 of 135 statements.
[2025-04-28 21:21:51,719 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-04-28 21:21:51,720 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-04-28 21:21:51,799 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-04-28 21:21:51,799 INFO  L340         BasicCegarLoop]: Counterexample is feasible
[2025-04-28 21:21:51,801 INFO  L790   garLoopResultBuilder]: Registering result UNSAFE for location Ultimate.STARTErr0ASSERT_VIOLATIONCHC_SATISFIABILITY (0 of 1 remaining)
[2025-04-28 21:21:51,803 WARN  L466      AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2
[2025-04-28 21:21:51,807 INFO  L422         BasicCegarLoop]: Path program histogram: [1, 1]
[2025-04-28 21:21:51,868 INFO  L171   ceAbstractionStarter]: Computing trace abstraction results
[2025-04-28 21:21:51,878 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.04 09:21:51 BoogieIcfgContainer
[2025-04-28 21:21:51,878 INFO  L131        PluginConnector]: ------------------------ END TraceAbstraction----------------------------
[2025-04-28 21:21:51,879 INFO  L158              Benchmark]: Toolchain (without parser) took 2596.05ms. Allocated memory is still 234.9MB. Free memory was 157.1MB in the beginning and 165.2MB in the end (delta: -8.1MB). There was no memory consumed. Max. memory is 33.6GB.
[2025-04-28 21:21:51,881 INFO  L158              Benchmark]: SmtParser took 0.39ms. Allocated memory is still 234.9MB. Free memory is still 170.3MB. There was no memory consumed. Max. memory is 33.6GB.
[2025-04-28 21:21:51,882 INFO  L158              Benchmark]: ChcToBoogie took 53.41ms. Allocated memory is still 234.9MB. Free memory was 157.1MB in the beginning and 155.7MB in the end (delta: 1.3MB). There was no memory consumed. Max. memory is 33.6GB.
[2025-04-28 21:21:51,882 INFO  L158              Benchmark]: Boogie Preprocessor took 62.23ms. Allocated memory is still 234.9MB. Free memory was 155.7MB in the beginning and 153.0MB in the end (delta: 2.7MB). There was no memory consumed. Max. memory is 33.6GB.
[2025-04-28 21:21:51,882 INFO  L158              Benchmark]: RCFGBuilder took 421.81ms. Allocated memory is still 234.9MB. Free memory was 153.0MB in the beginning and 129.8MB in the end (delta: 23.3MB). Peak memory consumption was 33.6MB. Max. memory is 33.6GB.
[2025-04-28 21:21:51,883 INFO  L158              Benchmark]: TraceAbstraction took 2049.85ms. Allocated memory is still 234.9MB. Free memory was 129.1MB in the beginning and 165.2MB in the end (delta: -36.1MB). There was no memory consumed. Max. memory is 33.6GB.
[2025-04-28 21:21:51,884 INFO  L338   ainManager$Toolchain]: #######################  End [Toolchain 1] #######################
 --- Results ---
 * Results from de.uni_freiburg.informatik.ultimate.core:
  - StatisticsResult: Toolchain Benchmarks
    Benchmark results are:
 * SmtParser took 0.39ms. Allocated memory is still 234.9MB. Free memory is still 170.3MB. There was no memory consumed. Max. memory is 33.6GB.
 * ChcToBoogie took 53.41ms. Allocated memory is still 234.9MB. Free memory was 157.1MB in the beginning and 155.7MB in the end (delta: 1.3MB). There was no memory consumed. Max. memory is 33.6GB.
 * Boogie Preprocessor took 62.23ms. Allocated memory is still 234.9MB. Free memory was 155.7MB in the beginning and 153.0MB in the end (delta: 2.7MB). There was no memory consumed. Max. memory is 33.6GB.
 * RCFGBuilder took 421.81ms. Allocated memory is still 234.9MB. Free memory was 153.0MB in the beginning and 129.8MB in the end (delta: 23.3MB). Peak memory consumption was 33.6MB. Max. memory is 33.6GB.
 * TraceAbstraction took 2049.85ms. Allocated memory is still 234.9MB. Free memory was 129.1MB in the beginning and 165.2MB in the end (delta: -36.1MB). There was no memory consumed. Max. memory is 33.6GB.
 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
  - StatisticsResult: ErrorAutomatonStatistics
    NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0
  - CounterExampleResult [Unknown line] : the set of constraint Horn clauses is unsatisfiable
    the set of constraint Horn clauses is unsatisfiable
We found a FailurePath: 
[L0]  CALL  call False();
[L0]  CALL  call ERR();
[L0]        assume !hbv_ERR_R_1;
      VAL   [hbv_ERR_R_1=false]
[L0]  CALL  call MAIN(hbv_ERR_A_2, hbv_ERR_B_3, hbv_ERR_C_4, hbv_ERR_D_5, hbv_ERR_E_6, hbv_ERR_F_7, hbv_ERR_G_8, hbv_ERR_H_9, hbv_ERR_I_10, hbv_ERR_J_11, hbv_ERR_K_12, hbv_ERR_L_13, hbv_ERR_M_14, hbv_ERR_N_15, hbv_ERR_O_16, hbv_ERR_P_17, hbv_ERR_Q_18, hbv_ERR_R_1);
      VAL   [hhv_MAIN_A2_15=false, hhv_MAIN_B2_16=false, hhv_MAIN_C2_17=false, hhv_MAIN_L1_0=false, hhv_MAIN_M1_1=true, hhv_MAIN_N1_2=false, hhv_MAIN_O1_3=false, hhv_MAIN_P1_4=true, hhv_MAIN_Q1_5=false, hhv_MAIN_R1_6=false, hhv_MAIN_S1_7=false, hhv_MAIN_T1_8=true, hhv_MAIN_U1_9=false, hhv_MAIN_V1_10=true, hhv_MAIN_W1_11=false, hhv_MAIN_X1_12=false, hhv_MAIN_Y1_13=true, hhv_MAIN_Z1_14=false]
[L0]  CALL  call MAIN(hbv_MAIN_A_1, hbv_MAIN_B_2, hbv_MAIN_C_3, hbv_MAIN_D_4, hbv_MAIN_E_5, hbv_MAIN_F_6, hbv_MAIN_G_7, hbv_MAIN_H_8, hbv_MAIN_I_9, hbv_MAIN_J_10, hbv_MAIN_K_11, hbv_MAIN_L_12, hbv_MAIN_M_13, hbv_MAIN_N_14, hbv_MAIN_O_15, hbv_MAIN_P_16, hbv_MAIN_Q_17, hbv_MAIN_U_18);
      VAL   [hhv_MAIN_A2_15=true, hhv_MAIN_B2_16=false, hhv_MAIN_C2_17=true, hhv_MAIN_L1_0=true, hhv_MAIN_M1_1=false, hhv_MAIN_N1_2=true, hhv_MAIN_O1_3=false, hhv_MAIN_P1_4=false, hhv_MAIN_Q1_5=false, hhv_MAIN_R1_6=false, hhv_MAIN_S1_7=false, hhv_MAIN_T1_8=false, hhv_MAIN_U1_9=false, hhv_MAIN_V1_10=true, hhv_MAIN_W1_11=false, hhv_MAIN_X1_12=false, hhv_MAIN_Y1_13=false, hhv_MAIN_Z1_14=false]
[L0]  CALL  call INIT_STATE();
[L0]  RET   call INIT_STATE();
      VAL   [hhv_MAIN_A2_15=true, hhv_MAIN_B2_16=false, hhv_MAIN_C2_17=true, hhv_MAIN_L1_0=true, hhv_MAIN_M1_1=false, hhv_MAIN_N1_2=true, hhv_MAIN_O1_3=false, hhv_MAIN_P1_4=false, hhv_MAIN_Q1_5=false, hhv_MAIN_R1_6=false, hhv_MAIN_S1_7=false, hhv_MAIN_T1_8=false, hhv_MAIN_U1_9=false, hhv_MAIN_V1_10=true, hhv_MAIN_W1_11=false, hhv_MAIN_X1_12=false, hhv_MAIN_Y1_13=false, hhv_MAIN_Z1_14=false]
[L0]  CALL  call top_reset(hbv_MAIN_A_1, hbv_MAIN_B_2, hbv_MAIN_C_3, hbv_MAIN_D_4, hbv_MAIN_E_5, hbv_MAIN_F_6, hbv_MAIN_G_7, hbv_MAIN_H_8, hbv_MAIN_I_9, hbv_MAIN_J_10, hbv_MAIN_K_11, hbv_MAIN_L_12, hbv_MAIN_M_13, hbv_MAIN_N_14, hbv_MAIN_O_15, hbv_MAIN_P_16, hbv_MAIN_Q_17, hbv_MAIN_U_18, hbv_MAIN_V_19, hbv_MAIN_W_20, hbv_MAIN_X_21, hbv_MAIN_Y_22, hbv_MAIN_Z_23, hbv_MAIN_A1_24, hbv_MAIN_B1_25, hbv_MAIN_C1_26, hbv_MAIN_D1_27, hbv_MAIN_E1_28, hbv_MAIN_F1_29, hbv_MAIN_G1_30, hbv_MAIN_H1_31, hbv_MAIN_I1_32, hbv_MAIN_J1_33, hbv_MAIN_K1_34);
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]        assume (!((hhv_top_reset_B_1 || hhv_top_reset_S_18) && (!hhv_top_reset_B_1 || !hhv_top_reset_S_18)) && !!hhv_top_reset_D1_29) && !((hhv_top_reset_A_0 || hhv_top_reset_R_17) && (!hhv_top_reset_R_17 || !hhv_top_reset_A_0));
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]  CALL  call redge_reset(hhv_top_reset_I_8, hhv_top_reset_J_9, hhv_top_reset_Z_25, hhv_top_reset_A1_26);
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]        assume !((hhv_redge_reset_C_2 || hhv_redge_reset_A_0) && (!hhv_redge_reset_A_0 || !hhv_redge_reset_C_2)) && !!hhv_redge_reset_D_3;
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]  RET   call redge_reset(hhv_top_reset_I_8, hhv_top_reset_J_9, hhv_top_reset_Z_25, hhv_top_reset_A1_26);
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]  CALL  call fedge_reset(hhv_top_reset_N_13, hhv_top_reset_O_14, hhv_top_reset_E1_30, hhv_top_reset_F1_31);
      VAL   [hhv_fedge_reset_A_0=false, hhv_fedge_reset_B_1=false, hhv_fedge_reset_C_2=false, hhv_fedge_reset_D_3=true]
[L0]  CALL  call redge_reset(hhv_fedge_reset_A_0, hhv_fedge_reset_B_1, hhv_fedge_reset_C_2, hhv_fedge_reset_D_3);
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]        assume !((hhv_redge_reset_C_2 || hhv_redge_reset_A_0) && (!hhv_redge_reset_A_0 || !hhv_redge_reset_C_2)) && !!hhv_redge_reset_D_3;
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]  RET   call redge_reset(hhv_fedge_reset_A_0, hhv_fedge_reset_B_1, hhv_fedge_reset_C_2, hhv_fedge_reset_D_3);
      VAL   [hhv_fedge_reset_A_0=false, hhv_fedge_reset_B_1=false, hhv_fedge_reset_C_2=false, hhv_fedge_reset_D_3=true]
[L0]  RET   call fedge_reset(hhv_top_reset_N_13, hhv_top_reset_O_14, hhv_top_reset_E1_30, hhv_top_reset_F1_31);
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]  CALL  call redge_reset(hhv_top_reset_K_10, hhv_top_reset_L_11, hhv_top_reset_B1_27, hhv_top_reset_C1_28);
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]        assume !((hhv_redge_reset_C_2 || hhv_redge_reset_A_0) && (!hhv_redge_reset_A_0 || !hhv_redge_reset_C_2)) && !!hhv_redge_reset_D_3;
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]  RET   call redge_reset(hhv_top_reset_K_10, hhv_top_reset_L_11, hhv_top_reset_B1_27, hhv_top_reset_C1_28);
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]  CALL  call redge_reset(hhv_top_reset_C_2, hhv_top_reset_D_3, hhv_top_reset_T_19, hhv_top_reset_U_20);
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]        assume !((hhv_redge_reset_C_2 || hhv_redge_reset_A_0) && (!hhv_redge_reset_A_0 || !hhv_redge_reset_C_2)) && !!hhv_redge_reset_D_3;
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]  RET   call redge_reset(hhv_top_reset_C_2, hhv_top_reset_D_3, hhv_top_reset_T_19, hhv_top_reset_U_20);
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]  CALL  call fedge_reset(hhv_top_reset_P_15, hhv_top_reset_Q_16, hhv_top_reset_G1_32, hhv_top_reset_H1_33);
      VAL   [hhv_fedge_reset_A_0=false, hhv_fedge_reset_B_1=true, hhv_fedge_reset_C_2=false, hhv_fedge_reset_D_3=true]
[L0]  CALL  call redge_reset(hhv_fedge_reset_A_0, hhv_fedge_reset_B_1, hhv_fedge_reset_C_2, hhv_fedge_reset_D_3);
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]        assume !((hhv_redge_reset_C_2 || hhv_redge_reset_A_0) && (!hhv_redge_reset_A_0 || !hhv_redge_reset_C_2)) && !!hhv_redge_reset_D_3;
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]  RET   call redge_reset(hhv_fedge_reset_A_0, hhv_fedge_reset_B_1, hhv_fedge_reset_C_2, hhv_fedge_reset_D_3);
      VAL   [hhv_fedge_reset_A_0=false, hhv_fedge_reset_B_1=true, hhv_fedge_reset_C_2=false, hhv_fedge_reset_D_3=true]
[L0]  RET   call fedge_reset(hhv_top_reset_P_15, hhv_top_reset_Q_16, hhv_top_reset_G1_32, hhv_top_reset_H1_33);
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]  CALL  call redge_reset(hhv_top_reset_E_4, hhv_top_reset_F_5, hhv_top_reset_V_21, hhv_top_reset_W_22);
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]        assume !((hhv_redge_reset_C_2 || hhv_redge_reset_A_0) && (!hhv_redge_reset_A_0 || !hhv_redge_reset_C_2)) && !!hhv_redge_reset_D_3;
      VAL   [hhv_redge_reset_A_0=false, hhv_redge_reset_C_2=false, hhv_redge_reset_D_3=true]
[L0]  RET   call redge_reset(hhv_top_reset_E_4, hhv_top_reset_F_5, hhv_top_reset_V_21, hhv_top_reset_W_22);
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]  CALL  call sustain_reset(hhv_top_reset_G_6, hhv_top_reset_H_7, hhv_top_reset_X_23, hhv_top_reset_Y_24);
      VAL   [hhv_sustain_reset_A_0=false, hhv_sustain_reset_C_2=false, hhv_sustain_reset_D_3=true]
[L0]        assume !!hhv_sustain_reset_D_3 && !((hhv_sustain_reset_C_2 || hhv_sustain_reset_A_0) && (!hhv_sustain_reset_A_0 || !hhv_sustain_reset_C_2));
      VAL   [hhv_sustain_reset_A_0=false, hhv_sustain_reset_C_2=false, hhv_sustain_reset_D_3=true]
[L0]  RET   call sustain_reset(hhv_top_reset_G_6, hhv_top_reset_H_7, hhv_top_reset_X_23, hhv_top_reset_Y_24);
      VAL   [hhv_top_reset_A1_26=true, hhv_top_reset_A_0=true, hhv_top_reset_B1_27=false, hhv_top_reset_B_1=false, hhv_top_reset_C1_28=true, hhv_top_reset_C_2=false, hhv_top_reset_D1_29=true, hhv_top_reset_D_3=true, hhv_top_reset_E1_30=false, hhv_top_reset_E_4=false, hhv_top_reset_F1_31=true, hhv_top_reset_F_5=false, hhv_top_reset_G1_32=false, hhv_top_reset_G_6=false, hhv_top_reset_H1_33=true, hhv_top_reset_H_7=false, hhv_top_reset_I_8=false, hhv_top_reset_J_9=false, hhv_top_reset_K_10=false, hhv_top_reset_L_11=false, hhv_top_reset_N_13=false, hhv_top_reset_O_14=false, hhv_top_reset_P_15=false, hhv_top_reset_Q_16=true, hhv_top_reset_R_17=true, hhv_top_reset_S_18=false, hhv_top_reset_T_19=false, hhv_top_reset_U_20=true, hhv_top_reset_V_21=false, hhv_top_reset_W_22=true, hhv_top_reset_X_23=false, hhv_top_reset_Y_24=true, hhv_top_reset_Z_25=false]
[L0]  RET   call top_reset(hbv_MAIN_A_1, hbv_MAIN_B_2, hbv_MAIN_C_3, hbv_MAIN_D_4, hbv_MAIN_E_5, hbv_MAIN_F_6, hbv_MAIN_G_7, hbv_MAIN_H_8, hbv_MAIN_I_9, hbv_MAIN_J_10, hbv_MAIN_K_11, hbv_MAIN_L_12, hbv_MAIN_M_13, hbv_MAIN_N_14, hbv_MAIN_O_15, hbv_MAIN_P_16, hbv_MAIN_Q_17, hbv_MAIN_U_18, hbv_MAIN_V_19, hbv_MAIN_W_20, hbv_MAIN_X_21, hbv_MAIN_Y_22, hbv_MAIN_Z_23, hbv_MAIN_A1_24, hbv_MAIN_B1_25, hbv_MAIN_C1_26, hbv_MAIN_D1_27, hbv_MAIN_E1_28, hbv_MAIN_F1_29, hbv_MAIN_G1_30, hbv_MAIN_H1_31, hbv_MAIN_I1_32, hbv_MAIN_J1_33, hbv_MAIN_K1_34);
      VAL   [hbv_MAIN_A1_24=false, hbv_MAIN_A_1=true, hbv_MAIN_B1_25=true, hbv_MAIN_B_2=false, hbv_MAIN_C1_26=false, hbv_MAIN_C_3=false, hbv_MAIN_D1_27=true, hbv_MAIN_D_4=true, hbv_MAIN_E1_28=false, hbv_MAIN_E_5=false, hbv_MAIN_F1_29=true, hbv_MAIN_F_6=false, hbv_MAIN_G1_30=true, hbv_MAIN_G_7=false, hbv_MAIN_H1_31=false, hbv_MAIN_H_8=false, hbv_MAIN_I1_32=true, hbv_MAIN_I_9=false, hbv_MAIN_J1_33=false, hbv_MAIN_J_10=false, hbv_MAIN_K1_34=true, hbv_MAIN_K_11=false, hbv_MAIN_L_12=false, hbv_MAIN_M_13=false, hbv_MAIN_N_14=false, hbv_MAIN_O_15=false, hbv_MAIN_P_16=false, hbv_MAIN_Q_17=true, hbv_MAIN_U_18=true, hbv_MAIN_V_19=false, hbv_MAIN_W_20=false, hbv_MAIN_X_21=true, hbv_MAIN_Y_22=false, hbv_MAIN_Z_23=true, hhv_MAIN_A2_15=true, hhv_MAIN_B2_16=false, hhv_MAIN_C2_17=true, hhv_MAIN_L1_0=true, hhv_MAIN_M1_1=false, hhv_MAIN_N1_2=true, hhv_MAIN_O1_3=false, hhv_MAIN_P1_4=false, hhv_MAIN_Q1_5=false, hhv_MAIN_R1_6=false, hhv_MAIN_S1_7=false, hhv_MAIN_T1_8=false, hhv_MAIN_U1_9=false, hhv_MAIN_V1_10=true, hhv_MAIN_W1_11=false, hhv_MAIN_X1_12=false, hhv_MAIN_Y1_13=false, hhv_MAIN_Z1_14=false]
[L0]  CALL  call top_step(hbv_MAIN_R_35, hbv_MAIN_S_36, hbv_MAIN_T_37, hhv_MAIN_C2_17, hbv_MAIN_U_18, hbv_MAIN_V_19, hbv_MAIN_W_20, hbv_MAIN_X_21, hbv_MAIN_Y_22, hbv_MAIN_Z_23, hbv_MAIN_A1_24, hbv_MAIN_B1_25, hbv_MAIN_C1_26, hbv_MAIN_D1_27, hbv_MAIN_E1_28, hbv_MAIN_F1_29, hbv_MAIN_G1_30, hbv_MAIN_H1_31, hbv_MAIN_I1_32, hbv_MAIN_J1_33, hbv_MAIN_K1_34, hhv_MAIN_L1_0, hhv_MAIN_M1_1, hhv_MAIN_N1_2, hhv_MAIN_O1_3, hhv_MAIN_P1_4, hhv_MAIN_Q1_5, hhv_MAIN_R1_6, hhv_MAIN_S1_7, hhv_MAIN_T1_8, hhv_MAIN_U1_9, hhv_MAIN_V1_10, hhv_MAIN_W1_11, hhv_MAIN_X1_12, hhv_MAIN_Y1_13, hhv_MAIN_Z1_14, hhv_MAIN_A2_15, hhv_MAIN_B2_16);
      VAL   [hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]        assume (((((((((((((((((((((((((((((((((!((!hbv_top_step_Z_11 && (hhv_top_step_L1_5 || hbv_top_step_L_24)) && (!hbv_top_step_L_24 || !hhv_top_step_L1_5)) && !(!hbv_top_step_U_5 && !hbv_top_step_D1_6)) && !((hhv_top_step_N1_7 || hbv_top_step_Y_1) && (!hhv_top_step_N1_7 || !hbv_top_step_Y_1))) && !((!hbv_top_step_D_12 || !hhv_top_step_Z1_19) && (hhv_top_step_Z1_19 || hbv_top_step_D_12))) && !((hhv_top_step_Q1_10 || hbv_top_step_S_9) && (!hbv_top_step_S_9 || !hhv_top_step_Q1_10))) && !((hhv_top_step_M1_6 || hbv_top_step_X_29) && (!hbv_top_step_X_29 || !hhv_top_step_M1_6))) && !((hbv_top_step_A_21 || (hbv_top_step_A1_15 && hbv_top_step_B1_14)) && ((!hbv_top_step_B1_14 || !hbv_top_step_A_21) || !hbv_top_step_A1_15))) && !((hhv_top_step_T1_13 || hbv_top_step_R_10) && (!hhv_top_step_T1_13 || !hbv_top_step_R_10))) && !((hhv_top_step_R1_11 || hbv_top_step_T_25) && (!hbv_top_step_T_25 || !hhv_top_step_R1_11))) && !((!hbv_top_step_G_32 || !hhv_top_step_Y1_18) && (hhv_top_step_Y1_18 || hbv_top_step_G_32))) && !((!hhv_top_step_S1_12 || !hbv_top_step_Q_27) && (hhv_top_step_S1_12 || hbv_top_step_Q_27))) && !(!hbv_top_step_P_22 && hbv_top_step_Z_11)) && !((!hhv_top_step_A2_20 || !hbv_top_step_E_8) && (hhv_top_step_A2_20 || hbv_top_step_E_8))) && !((hhv_top_step_O1_8 || hbv_top_step_V_19) && (!hhv_top_step_O1_8 || !hbv_top_step_V_19))) && !((!hbv_top_step_J_23 || !hhv_top_step_W1_16) && (hhv_top_step_W1_16 || hbv_top_step_J_23))) && !(hhv_top_step_I1_2 && hhv_top_step_B2_21)) && !(!hhv_top_step_J1_3 && hbv_top_step_Z_11)) && !(!hbv_top_step_Z_11 && (((!hhv_top_step_J1_3 && hbv_top_step_E1_17) && hbv_top_step_F1_16) || (((((!hhv_top_step_J1_3 || (((hbv_top_step_B1_14 || hbv_top_step_C1_4) && (hbv_top_step_A1_15 || hbv_top_step_C1_4)) && (hbv_top_step_A1_15 || hbv_top_step_B1_14))) || ((hbv_top_step_A1_15 && hbv_top_step_B1_14) && hbv_top_step_C1_4)) || !hbv_top_step_D1_6) && (hhv_top_step_J1_3 || ((hbv_top_step_D1_6 && (((!hbv_top_step_B1_14 && !hbv_top_step_A1_15) || (!hbv_top_step_C1_4 && !hbv_top_step_A1_15)) || (!hbv_top_step_C1_4 && !hbv_top_step_B1_14))) && ((!hbv_top_step_C1_4 || !hbv_top_step_B1_14) || !hbv_top_step_A1_15)))) && (!hbv_top_step_F1_16 || !hbv_top_step_E1_17))))) && !(((hbv_top_step_O_18 && hbv_top_step_P_22) || hbv_top_step_B_30) && ((!hbv_top_step_B_30 || !hbv_top_step_P_22) || !hbv_top_step_O_18))) && !((!hbv_top_step_J_23 || !hbv_top_step_Z_11) && (hbv_top_step_J_23 || hbv_top_step_Z_11))) && !(!hbv_top_step_L_24 && hbv_top_step_Z_11)) && !hhv_top_step_N2_33) && !((hbv_top_step_U_5 && (hbv_top_step_D1_6 || hhv_top_step_G1_0)) && (!hhv_top_step_G1_0 || !hbv_top_step_D1_6))) && !((!hbv_top_step_C1_4 || (!hbv_top_step_H_2 && !hbv_top_step_I_3)) && ((hbv_top_step_C1_4 || hbv_top_step_H_2) || hbv_top_step_I_3))) && !((hbv_top_step_O_18 || (hhv_top_step_G1_0 && hhv_top_step_H1_1)) && ((!hbv_top_step_O_18 || !hhv_top_step_G1_0) || !hhv_top_step_H1_1))) && !(!hhv_top_step_I1_2 && !hhv_top_step_B2_21)) && !(!hhv_top_step_H1_1 && !hhv_top_step_C2_22)) && !((!hbv_top_step_W_31 || !hhv_top_step_P1_9) && (hhv_top_step_P1_9 || hbv_top_step_W_31))) && !((hhv_top_step_X1_17 || hbv_top_step_F_7) && (!hbv_top_step_F_7 || !hhv_top_step_X1_17))) && !(((!hhv_top_step_G1_0 || !hbv_top_step_K_13) || !hhv_top_step_I1_2) && ((hhv_top_step_I1_2 && hhv_top_step_G1_0) || hbv_top_step_K_13))) && !((hbv_top_step_C_28 || (hbv_top_step_K_13 && hbv_top_step_L_24)) && ((!hbv_top_step_L_24 || !hbv_top_step_K_13) || !hbv_top_step_C_28))) && !((hhv_top_step_V1_15 || hbv_top_step_N_26) && (!hbv_top_step_N_26 || !hhv_top_step_V1_15))) && !(((!hbv_top_step_P_22 || !hhv_top_step_K1_4) && (hhv_top_step_K1_4 || hbv_top_step_P_22)) && !hbv_top_step_Z_11)) && !((!hbv_top_step_M_20 || !hhv_top_step_U1_14) && (hhv_top_step_U1_14 || hbv_top_step_M_20))) && !(hhv_top_step_C2_22 && hhv_top_step_H1_1);
      VAL   [hbv_top_step_A1_15=true, hbv_top_step_A_21=false, hbv_top_step_B1_14=false, hbv_top_step_B_30=true, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=false, hbv_top_step_E1_17=true, hbv_top_step_E_8=true, hbv_top_step_F1_16=false, hbv_top_step_F_7=false, hbv_top_step_G_32=true, hbv_top_step_H_2=false, hbv_top_step_I_3=true, hbv_top_step_K_13=false, hbv_top_step_M_20=false, hbv_top_step_N_26=true, hbv_top_step_O_18=true, hbv_top_step_Q_27=false, hbv_top_step_R_10=true, hbv_top_step_S_9=false, hbv_top_step_T_25=true, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=true, hbv_top_step_X_29=false, hbv_top_step_Y_1=true, hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]  CALL  call redge_step(hhv_top_step_I1_2, hbv_top_step_F1_16, hbv_top_step_X_29, hbv_top_step_Y_1, hhv_top_step_D2_23, hhv_top_step_E2_24);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hhv_top_step_I1_2, hbv_top_step_F1_16, hbv_top_step_X_29, hbv_top_step_Y_1, hhv_top_step_D2_23, hhv_top_step_E2_24);
      VAL   [hbv_top_step_A1_15=true, hbv_top_step_A_21=false, hbv_top_step_B1_14=false, hbv_top_step_B_30=true, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=false, hbv_top_step_E1_17=true, hbv_top_step_E_8=true, hbv_top_step_F1_16=false, hbv_top_step_F_7=false, hbv_top_step_G_32=true, hbv_top_step_H_2=false, hbv_top_step_I_3=true, hbv_top_step_K_13=false, hbv_top_step_M_20=false, hbv_top_step_N_26=true, hbv_top_step_O_18=true, hbv_top_step_Q_27=false, hbv_top_step_R_10=true, hbv_top_step_S_9=false, hbv_top_step_T_25=true, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=true, hbv_top_step_X_29=false, hbv_top_step_Y_1=true, hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]  CALL  call fedge_step(hbv_top_step_O_18, hbv_top_step_H_2, hbv_top_step_D_12, hbv_top_step_E_8, hhv_top_step_Q2_36, hhv_top_step_R2_37);
      VAL   [hhv_fedge_step_D_0=true, hhv_fedge_step_E_1=false, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=true, hhv_fedge_step_H_4=true, hhv_fedge_step_I_5=false]
[L0]        assume ((!(!hhv_fedge_step_D_0 && !hbv_fedge_step_A_1) && !((!hhv_fedge_step_G_3 || !hbv_fedge_step_C_3) && (hbv_fedge_step_C_3 || hhv_fedge_step_G_3))) && !((!hbv_fedge_step_B_2 || !hhv_fedge_step_F_2) && (hbv_fedge_step_B_2 || hhv_fedge_step_F_2))) && !(hbv_fedge_step_A_1 && hhv_fedge_step_D_0);
      VAL   [hbv_fedge_step_A_1=false, hbv_fedge_step_B_2=false, hbv_fedge_step_C_3=true, hhv_fedge_step_D_0=true, hhv_fedge_step_E_1=false, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=true, hhv_fedge_step_H_4=true, hhv_fedge_step_I_5=false]
[L0]  CALL  call redge_step(hbv_fedge_step_A_1, hhv_fedge_step_E_1, hbv_fedge_step_B_2, hbv_fedge_step_C_3, hhv_fedge_step_H_4, hhv_fedge_step_I_5);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hbv_fedge_step_A_1, hhv_fedge_step_E_1, hbv_fedge_step_B_2, hbv_fedge_step_C_3, hhv_fedge_step_H_4, hhv_fedge_step_I_5);
      VAL   [hbv_fedge_step_A_1=false, hbv_fedge_step_B_2=false, hbv_fedge_step_C_3=true, hhv_fedge_step_D_0=true, hhv_fedge_step_E_1=false, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=true, hhv_fedge_step_H_4=true, hhv_fedge_step_I_5=false]
[L0]  RET   call fedge_step(hbv_top_step_O_18, hbv_top_step_H_2, hbv_top_step_D_12, hbv_top_step_E_8, hhv_top_step_Q2_36, hhv_top_step_R2_37);
      VAL   [hbv_top_step_A1_15=true, hbv_top_step_A_21=false, hbv_top_step_B1_14=false, hbv_top_step_B_30=true, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=false, hbv_top_step_E1_17=true, hbv_top_step_E_8=true, hbv_top_step_F1_16=false, hbv_top_step_F_7=false, hbv_top_step_G_32=true, hbv_top_step_H_2=false, hbv_top_step_I_3=true, hbv_top_step_K_13=false, hbv_top_step_M_20=false, hbv_top_step_N_26=true, hbv_top_step_O_18=true, hbv_top_step_Q_27=false, hbv_top_step_R_10=true, hbv_top_step_S_9=false, hbv_top_step_T_25=true, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=true, hbv_top_step_X_29=false, hbv_top_step_Y_1=true, hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]  CALL  call fedge_step(hbv_top_step_K_13, hbv_top_step_I_3, hbv_top_step_F_7, hbv_top_step_G_32, hhv_top_step_O2_34, hhv_top_step_P2_35);
      VAL   [hhv_fedge_step_D_0=false, hhv_fedge_step_E_1=true, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=true, hhv_fedge_step_H_4=false, hhv_fedge_step_I_5=false]
[L0]        assume ((!(!hhv_fedge_step_D_0 && !hbv_fedge_step_A_1) && !((!hhv_fedge_step_G_3 || !hbv_fedge_step_C_3) && (hbv_fedge_step_C_3 || hhv_fedge_step_G_3))) && !((!hbv_fedge_step_B_2 || !hhv_fedge_step_F_2) && (hbv_fedge_step_B_2 || hhv_fedge_step_F_2))) && !(hbv_fedge_step_A_1 && hhv_fedge_step_D_0);
      VAL   [hbv_fedge_step_A_1=true, hbv_fedge_step_B_2=false, hbv_fedge_step_C_3=true, hhv_fedge_step_D_0=false, hhv_fedge_step_E_1=true, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=true, hhv_fedge_step_H_4=false, hhv_fedge_step_I_5=false]
[L0]  CALL  call redge_step(hbv_fedge_step_A_1, hhv_fedge_step_E_1, hbv_fedge_step_B_2, hbv_fedge_step_C_3, hhv_fedge_step_H_4, hhv_fedge_step_I_5);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hbv_fedge_step_A_1, hhv_fedge_step_E_1, hbv_fedge_step_B_2, hbv_fedge_step_C_3, hhv_fedge_step_H_4, hhv_fedge_step_I_5);
      VAL   [hbv_fedge_step_A_1=true, hbv_fedge_step_B_2=false, hbv_fedge_step_C_3=true, hhv_fedge_step_D_0=false, hhv_fedge_step_E_1=true, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=true, hhv_fedge_step_H_4=false, hhv_fedge_step_I_5=false]
[L0]  RET   call fedge_step(hbv_top_step_K_13, hbv_top_step_I_3, hbv_top_step_F_7, hbv_top_step_G_32, hhv_top_step_O2_34, hhv_top_step_P2_35);
      VAL   [hbv_top_step_A1_15=true, hbv_top_step_A_21=false, hbv_top_step_B1_14=false, hbv_top_step_B_30=true, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=false, hbv_top_step_E1_17=true, hbv_top_step_E_8=true, hbv_top_step_F1_16=false, hbv_top_step_F_7=false, hbv_top_step_G_32=true, hbv_top_step_H_2=false, hbv_top_step_I_3=true, hbv_top_step_K_13=false, hbv_top_step_M_20=false, hbv_top_step_N_26=true, hbv_top_step_O_18=true, hbv_top_step_Q_27=false, hbv_top_step_R_10=true, hbv_top_step_S_9=false, hbv_top_step_T_25=true, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=true, hbv_top_step_X_29=false, hbv_top_step_Y_1=true, hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]  CALL  call redge_step(hbv_top_step_C_28, hbv_top_step_B1_14, hbv_top_step_M_20, hbv_top_step_N_26, hhv_top_step_L2_31, hhv_top_step_M2_32);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hbv_top_step_C_28, hbv_top_step_B1_14, hbv_top_step_M_20, hbv_top_step_N_26, hhv_top_step_L2_31, hhv_top_step_M2_32);
      VAL   [hbv_top_step_A1_15=true, hbv_top_step_A_21=false, hbv_top_step_B1_14=false, hbv_top_step_B_30=true, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=false, hbv_top_step_E1_17=true, hbv_top_step_E_8=true, hbv_top_step_F1_16=false, hbv_top_step_F_7=false, hbv_top_step_G_32=true, hbv_top_step_H_2=false, hbv_top_step_I_3=true, hbv_top_step_K_13=false, hbv_top_step_M_20=false, hbv_top_step_N_26=true, hbv_top_step_O_18=true, hbv_top_step_Q_27=false, hbv_top_step_R_10=true, hbv_top_step_S_9=false, hbv_top_step_T_25=true, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=true, hbv_top_step_X_29=false, hbv_top_step_Y_1=true, hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]  CALL  call redge_step(hbv_top_step_B_30, hbv_top_step_A1_15, hbv_top_step_Q_27, hbv_top_step_R_10, hhv_top_step_J2_29, hhv_top_step_K2_30);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hbv_top_step_B_30, hbv_top_step_A1_15, hbv_top_step_Q_27, hbv_top_step_R_10, hhv_top_step_J2_29, hhv_top_step_K2_30);
      VAL   [hbv_top_step_A1_15=true, hbv_top_step_A_21=false, hbv_top_step_B1_14=false, hbv_top_step_B_30=true, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=false, hbv_top_step_E1_17=true, hbv_top_step_E_8=true, hbv_top_step_F1_16=false, hbv_top_step_F_7=false, hbv_top_step_G_32=true, hbv_top_step_H_2=false, hbv_top_step_I_3=true, hbv_top_step_K_13=false, hbv_top_step_M_20=false, hbv_top_step_N_26=true, hbv_top_step_O_18=true, hbv_top_step_Q_27=false, hbv_top_step_R_10=true, hbv_top_step_S_9=false, hbv_top_step_T_25=true, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=true, hbv_top_step_X_29=false, hbv_top_step_Y_1=true, hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]  CALL  call redge_step(hhv_top_step_H1_1, hbv_top_step_E1_17, hbv_top_step_V_19, hbv_top_step_W_31, hhv_top_step_F2_25, hhv_top_step_G2_26);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=false, hhv_redge_step_F_3=true, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hhv_top_step_H1_1, hbv_top_step_E1_17, hbv_top_step_V_19, hbv_top_step_W_31, hhv_top_step_F2_25, hhv_top_step_G2_26);
      VAL   [hbv_top_step_A1_15=true, hbv_top_step_A_21=false, hbv_top_step_B1_14=false, hbv_top_step_B_30=true, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=false, hbv_top_step_E1_17=true, hbv_top_step_E_8=true, hbv_top_step_F1_16=false, hbv_top_step_F_7=false, hbv_top_step_G_32=true, hbv_top_step_H_2=false, hbv_top_step_I_3=true, hbv_top_step_K_13=false, hbv_top_step_M_20=false, hbv_top_step_N_26=true, hbv_top_step_O_18=true, hbv_top_step_Q_27=false, hbv_top_step_R_10=true, hbv_top_step_S_9=false, hbv_top_step_T_25=true, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=true, hbv_top_step_X_29=false, hbv_top_step_Y_1=true, hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]  CALL  call sustain_step(hbv_top_step_A_21, hbv_top_step_C1_4, hbv_top_step_U_5, hbv_top_step_S_9, hbv_top_step_T_25, hhv_top_step_H2_27, hhv_top_step_I2_28);
      VAL   [hhv_sustain_step_C_0=false, hhv_sustain_step_D_1=true, hhv_sustain_step_E_2=false, hhv_sustain_step_F_3=false, hhv_sustain_step_G_4=true, hhv_sustain_step_H_5=false, hhv_sustain_step_I_6=false]
[L0]        assume ((((!((!hhv_sustain_step_G_4 || !hbv_sustain_step_A_2) && (hbv_sustain_step_A_2 || hhv_sustain_step_G_4)) && !((hbv_sustain_step_B_1 && (!hhv_sustain_step_C_0 || !hhv_sustain_step_E_2)) && (hhv_sustain_step_C_0 || hhv_sustain_step_E_2))) && !((!hhv_sustain_step_H_5 || !hhv_sustain_step_E_2) && (hhv_sustain_step_H_5 || hhv_sustain_step_E_2))) && !((hbv_sustain_step_B_1 || hbv_sustain_step_A_2) && (!hbv_sustain_step_B_1 || !hbv_sustain_step_A_2))) && !hhv_sustain_step_I_6) && !(!hbv_sustain_step_B_1 && ((((((hhv_sustain_step_F_3 || hhv_sustain_step_E_2) && !hhv_sustain_step_D_1) && (!hhv_sustain_step_F_3 || !hhv_sustain_step_E_2)) || (hhv_sustain_step_D_1 && hhv_sustain_step_E_2)) && !hhv_sustain_step_C_0) || (hhv_sustain_step_C_0 && !hhv_sustain_step_E_2)));
      VAL   [hhv_sustain_step_C_0=false, hhv_sustain_step_D_1=true, hhv_sustain_step_E_2=false, hhv_sustain_step_F_3=false, hhv_sustain_step_G_4=true, hhv_sustain_step_H_5=false, hhv_sustain_step_I_6=false]
[L0]  RET   call sustain_step(hbv_top_step_A_21, hbv_top_step_C1_4, hbv_top_step_U_5, hbv_top_step_S_9, hbv_top_step_T_25, hhv_top_step_H2_27, hhv_top_step_I2_28);
      VAL   [hbv_top_step_A1_15=true, hbv_top_step_A_21=false, hbv_top_step_B1_14=false, hbv_top_step_B_30=true, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=false, hbv_top_step_E1_17=true, hbv_top_step_E_8=true, hbv_top_step_F1_16=false, hbv_top_step_F_7=false, hbv_top_step_G_32=true, hbv_top_step_H_2=false, hbv_top_step_I_3=true, hbv_top_step_K_13=false, hbv_top_step_M_20=false, hbv_top_step_N_26=true, hbv_top_step_O_18=true, hbv_top_step_Q_27=false, hbv_top_step_R_10=true, hbv_top_step_S_9=false, hbv_top_step_T_25=true, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=true, hbv_top_step_X_29=false, hbv_top_step_Y_1=true, hhv_top_step_A2_20=true, hhv_top_step_B2_21=true, hhv_top_step_C2_22=false, hhv_top_step_D2_23=true, hhv_top_step_E2_24=false, hhv_top_step_F2_25=false, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=true, hhv_top_step_H2_27=false, hhv_top_step_I1_2=false, hhv_top_step_I2_28=false, hhv_top_step_J1_3=true, hhv_top_step_J2_29=false, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=false, hhv_top_step_M2_32=false, hhv_top_step_N1_7=true, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=false, hhv_top_step_P1_9=true, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=true, hhv_top_step_R1_11=true, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=true, hhv_top_step_U1_14=false, hhv_top_step_V1_15=true, hhv_top_step_W1_16=true, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=true, hhv_top_step_Z1_19=false]
[L0]  RET   call top_step(hbv_MAIN_R_35, hbv_MAIN_S_36, hbv_MAIN_T_37, hhv_MAIN_C2_17, hbv_MAIN_U_18, hbv_MAIN_V_19, hbv_MAIN_W_20, hbv_MAIN_X_21, hbv_MAIN_Y_22, hbv_MAIN_Z_23, hbv_MAIN_A1_24, hbv_MAIN_B1_25, hbv_MAIN_C1_26, hbv_MAIN_D1_27, hbv_MAIN_E1_28, hbv_MAIN_F1_29, hbv_MAIN_G1_30, hbv_MAIN_H1_31, hbv_MAIN_I1_32, hbv_MAIN_J1_33, hbv_MAIN_K1_34, hhv_MAIN_L1_0, hhv_MAIN_M1_1, hhv_MAIN_N1_2, hhv_MAIN_O1_3, hhv_MAIN_P1_4, hhv_MAIN_Q1_5, hhv_MAIN_R1_6, hhv_MAIN_S1_7, hhv_MAIN_T1_8, hhv_MAIN_U1_9, hhv_MAIN_V1_10, hhv_MAIN_W1_11, hhv_MAIN_X1_12, hhv_MAIN_Y1_13, hhv_MAIN_Z1_14, hhv_MAIN_A2_15, hhv_MAIN_B2_16);
      VAL   [hbv_MAIN_A1_24=false, hbv_MAIN_A_1=true, hbv_MAIN_B1_25=true, hbv_MAIN_B_2=false, hbv_MAIN_C1_26=false, hbv_MAIN_C_3=false, hbv_MAIN_D1_27=true, hbv_MAIN_D_4=true, hbv_MAIN_E1_28=false, hbv_MAIN_E_5=false, hbv_MAIN_F1_29=true, hbv_MAIN_F_6=false, hbv_MAIN_G1_30=true, hbv_MAIN_G_7=false, hbv_MAIN_H1_31=false, hbv_MAIN_H_8=false, hbv_MAIN_I1_32=true, hbv_MAIN_I_9=false, hbv_MAIN_J1_33=false, hbv_MAIN_J_10=false, hbv_MAIN_K1_34=true, hbv_MAIN_K_11=false, hbv_MAIN_L_12=false, hbv_MAIN_M_13=false, hbv_MAIN_N_14=false, hbv_MAIN_O_15=false, hbv_MAIN_P_16=false, hbv_MAIN_Q_17=true, hbv_MAIN_R_35=true, hbv_MAIN_S_36=true, hbv_MAIN_T_37=false, hbv_MAIN_U_18=true, hbv_MAIN_V_19=false, hbv_MAIN_W_20=false, hbv_MAIN_X_21=true, hbv_MAIN_Y_22=false, hbv_MAIN_Z_23=true, hhv_MAIN_A2_15=true, hhv_MAIN_B2_16=false, hhv_MAIN_C2_17=true, hhv_MAIN_L1_0=true, hhv_MAIN_M1_1=false, hhv_MAIN_N1_2=true, hhv_MAIN_O1_3=false, hhv_MAIN_P1_4=false, hhv_MAIN_Q1_5=false, hhv_MAIN_R1_6=false, hhv_MAIN_S1_7=false, hhv_MAIN_T1_8=false, hhv_MAIN_U1_9=false, hhv_MAIN_V1_10=true, hhv_MAIN_W1_11=false, hhv_MAIN_X1_12=false, hhv_MAIN_Y1_13=false, hhv_MAIN_Z1_14=false]
[L0]  RET   call MAIN(hbv_MAIN_A_1, hbv_MAIN_B_2, hbv_MAIN_C_3, hbv_MAIN_D_4, hbv_MAIN_E_5, hbv_MAIN_F_6, hbv_MAIN_G_7, hbv_MAIN_H_8, hbv_MAIN_I_9, hbv_MAIN_J_10, hbv_MAIN_K_11, hbv_MAIN_L_12, hbv_MAIN_M_13, hbv_MAIN_N_14, hbv_MAIN_O_15, hbv_MAIN_P_16, hbv_MAIN_Q_17, hbv_MAIN_U_18);
      VAL   [hbv_MAIN_A_1=true, hbv_MAIN_B_2=false, hbv_MAIN_C_3=true, hbv_MAIN_D_4=false, hbv_MAIN_E_5=false, hbv_MAIN_F_6=false, hbv_MAIN_G_7=false, hbv_MAIN_H_8=false, hbv_MAIN_I_9=false, hbv_MAIN_J_10=false, hbv_MAIN_K_11=true, hbv_MAIN_L_12=false, hbv_MAIN_M_13=false, hbv_MAIN_N_14=false, hbv_MAIN_O_15=false, hbv_MAIN_P_16=true, hbv_MAIN_Q_17=false, hbv_MAIN_U_18=true, hhv_MAIN_A2_15=false, hhv_MAIN_B2_16=false, hhv_MAIN_C2_17=false, hhv_MAIN_L1_0=false, hhv_MAIN_M1_1=true, hhv_MAIN_N1_2=false, hhv_MAIN_O1_3=false, hhv_MAIN_P1_4=true, hhv_MAIN_Q1_5=false, hhv_MAIN_R1_6=false, hhv_MAIN_S1_7=false, hhv_MAIN_T1_8=true, hhv_MAIN_U1_9=false, hhv_MAIN_V1_10=true, hhv_MAIN_W1_11=false, hhv_MAIN_X1_12=false, hhv_MAIN_Y1_13=true, hhv_MAIN_Z1_14=false]
[L0]  CALL  call top_step(hbv_MAIN_V_19, hbv_MAIN_W_20, hbv_MAIN_X_21, hhv_MAIN_C2_17, hbv_MAIN_A_1, hbv_MAIN_B_2, hbv_MAIN_C_3, hbv_MAIN_D_4, hbv_MAIN_E_5, hbv_MAIN_F_6, hbv_MAIN_G_7, hbv_MAIN_H_8, hbv_MAIN_I_9, hbv_MAIN_J_10, hbv_MAIN_K_11, hbv_MAIN_L_12, hbv_MAIN_M_13, hbv_MAIN_N_14, hbv_MAIN_O_15, hbv_MAIN_P_16, hbv_MAIN_Q_17, hhv_MAIN_L1_0, hhv_MAIN_M1_1, hhv_MAIN_N1_2, hhv_MAIN_O1_3, hhv_MAIN_P1_4, hhv_MAIN_Q1_5, hhv_MAIN_R1_6, hhv_MAIN_S1_7, hhv_MAIN_T1_8, hhv_MAIN_U1_9, hhv_MAIN_V1_10, hhv_MAIN_W1_11, hhv_MAIN_X1_12, hhv_MAIN_Y1_13, hhv_MAIN_Z1_14, hhv_MAIN_A2_15, hhv_MAIN_B2_16);
      VAL   [hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]        assume (((((((((((((((((((((((((((((((((!((!hbv_top_step_Z_11 && (hhv_top_step_L1_5 || hbv_top_step_L_24)) && (!hbv_top_step_L_24 || !hhv_top_step_L1_5)) && !(!hbv_top_step_U_5 && !hbv_top_step_D1_6)) && !((hhv_top_step_N1_7 || hbv_top_step_Y_1) && (!hhv_top_step_N1_7 || !hbv_top_step_Y_1))) && !((!hbv_top_step_D_12 || !hhv_top_step_Z1_19) && (hhv_top_step_Z1_19 || hbv_top_step_D_12))) && !((hhv_top_step_Q1_10 || hbv_top_step_S_9) && (!hbv_top_step_S_9 || !hhv_top_step_Q1_10))) && !((hhv_top_step_M1_6 || hbv_top_step_X_29) && (!hbv_top_step_X_29 || !hhv_top_step_M1_6))) && !((hbv_top_step_A_21 || (hbv_top_step_A1_15 && hbv_top_step_B1_14)) && ((!hbv_top_step_B1_14 || !hbv_top_step_A_21) || !hbv_top_step_A1_15))) && !((hhv_top_step_T1_13 || hbv_top_step_R_10) && (!hhv_top_step_T1_13 || !hbv_top_step_R_10))) && !((hhv_top_step_R1_11 || hbv_top_step_T_25) && (!hbv_top_step_T_25 || !hhv_top_step_R1_11))) && !((!hbv_top_step_G_32 || !hhv_top_step_Y1_18) && (hhv_top_step_Y1_18 || hbv_top_step_G_32))) && !((!hhv_top_step_S1_12 || !hbv_top_step_Q_27) && (hhv_top_step_S1_12 || hbv_top_step_Q_27))) && !(!hbv_top_step_P_22 && hbv_top_step_Z_11)) && !((!hhv_top_step_A2_20 || !hbv_top_step_E_8) && (hhv_top_step_A2_20 || hbv_top_step_E_8))) && !((hhv_top_step_O1_8 || hbv_top_step_V_19) && (!hhv_top_step_O1_8 || !hbv_top_step_V_19))) && !((!hbv_top_step_J_23 || !hhv_top_step_W1_16) && (hhv_top_step_W1_16 || hbv_top_step_J_23))) && !(hhv_top_step_I1_2 && hhv_top_step_B2_21)) && !(!hhv_top_step_J1_3 && hbv_top_step_Z_11)) && !(!hbv_top_step_Z_11 && (((!hhv_top_step_J1_3 && hbv_top_step_E1_17) && hbv_top_step_F1_16) || (((((!hhv_top_step_J1_3 || (((hbv_top_step_B1_14 || hbv_top_step_C1_4) && (hbv_top_step_A1_15 || hbv_top_step_C1_4)) && (hbv_top_step_A1_15 || hbv_top_step_B1_14))) || ((hbv_top_step_A1_15 && hbv_top_step_B1_14) && hbv_top_step_C1_4)) || !hbv_top_step_D1_6) && (hhv_top_step_J1_3 || ((hbv_top_step_D1_6 && (((!hbv_top_step_B1_14 && !hbv_top_step_A1_15) || (!hbv_top_step_C1_4 && !hbv_top_step_A1_15)) || (!hbv_top_step_C1_4 && !hbv_top_step_B1_14))) && ((!hbv_top_step_C1_4 || !hbv_top_step_B1_14) || !hbv_top_step_A1_15)))) && (!hbv_top_step_F1_16 || !hbv_top_step_E1_17))))) && !(((hbv_top_step_O_18 && hbv_top_step_P_22) || hbv_top_step_B_30) && ((!hbv_top_step_B_30 || !hbv_top_step_P_22) || !hbv_top_step_O_18))) && !((!hbv_top_step_J_23 || !hbv_top_step_Z_11) && (hbv_top_step_J_23 || hbv_top_step_Z_11))) && !(!hbv_top_step_L_24 && hbv_top_step_Z_11)) && !hhv_top_step_N2_33) && !((hbv_top_step_U_5 && (hbv_top_step_D1_6 || hhv_top_step_G1_0)) && (!hhv_top_step_G1_0 || !hbv_top_step_D1_6))) && !((!hbv_top_step_C1_4 || (!hbv_top_step_H_2 && !hbv_top_step_I_3)) && ((hbv_top_step_C1_4 || hbv_top_step_H_2) || hbv_top_step_I_3))) && !((hbv_top_step_O_18 || (hhv_top_step_G1_0 && hhv_top_step_H1_1)) && ((!hbv_top_step_O_18 || !hhv_top_step_G1_0) || !hhv_top_step_H1_1))) && !(!hhv_top_step_I1_2 && !hhv_top_step_B2_21)) && !(!hhv_top_step_H1_1 && !hhv_top_step_C2_22)) && !((!hbv_top_step_W_31 || !hhv_top_step_P1_9) && (hhv_top_step_P1_9 || hbv_top_step_W_31))) && !((hhv_top_step_X1_17 || hbv_top_step_F_7) && (!hbv_top_step_F_7 || !hhv_top_step_X1_17))) && !(((!hhv_top_step_G1_0 || !hbv_top_step_K_13) || !hhv_top_step_I1_2) && ((hhv_top_step_I1_2 && hhv_top_step_G1_0) || hbv_top_step_K_13))) && !((hbv_top_step_C_28 || (hbv_top_step_K_13 && hbv_top_step_L_24)) && ((!hbv_top_step_L_24 || !hbv_top_step_K_13) || !hbv_top_step_C_28))) && !((hhv_top_step_V1_15 || hbv_top_step_N_26) && (!hbv_top_step_N_26 || !hhv_top_step_V1_15))) && !(((!hbv_top_step_P_22 || !hhv_top_step_K1_4) && (hhv_top_step_K1_4 || hbv_top_step_P_22)) && !hbv_top_step_Z_11)) && !((!hbv_top_step_M_20 || !hhv_top_step_U1_14) && (hhv_top_step_U1_14 || hbv_top_step_M_20))) && !(hhv_top_step_C2_22 && hhv_top_step_H1_1);
      VAL   [hbv_top_step_A1_15=false, hbv_top_step_A_21=false, hbv_top_step_B1_14=true, hbv_top_step_B_30=false, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=true, hbv_top_step_E1_17=false, hbv_top_step_E_8=false, hbv_top_step_F1_16=true, hbv_top_step_F_7=false, hbv_top_step_G_32=false, hbv_top_step_H_2=true, hbv_top_step_I_3=false, hbv_top_step_K_13=true, hbv_top_step_M_20=true, hbv_top_step_N_26=false, hbv_top_step_O_18=false, hbv_top_step_Q_27=false, hbv_top_step_R_10=false, hbv_top_step_S_9=false, hbv_top_step_T_25=false, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=false, hbv_top_step_X_29=true, hbv_top_step_Y_1=false, hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]  CALL  call redge_step(hhv_top_step_I1_2, hbv_top_step_F1_16, hbv_top_step_X_29, hbv_top_step_Y_1, hhv_top_step_D2_23, hhv_top_step_E2_24);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=true, hhv_redge_step_F_3=false, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=true, hhv_redge_step_F_3=false, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hhv_top_step_I1_2, hbv_top_step_F1_16, hbv_top_step_X_29, hbv_top_step_Y_1, hhv_top_step_D2_23, hhv_top_step_E2_24);
      VAL   [hbv_top_step_A1_15=false, hbv_top_step_A_21=false, hbv_top_step_B1_14=true, hbv_top_step_B_30=false, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=true, hbv_top_step_E1_17=false, hbv_top_step_E_8=false, hbv_top_step_F1_16=true, hbv_top_step_F_7=false, hbv_top_step_G_32=false, hbv_top_step_H_2=true, hbv_top_step_I_3=false, hbv_top_step_K_13=true, hbv_top_step_M_20=true, hbv_top_step_N_26=false, hbv_top_step_O_18=false, hbv_top_step_Q_27=false, hbv_top_step_R_10=false, hbv_top_step_S_9=false, hbv_top_step_T_25=false, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=false, hbv_top_step_X_29=true, hbv_top_step_Y_1=false, hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]  CALL  call fedge_step(hbv_top_step_O_18, hbv_top_step_H_2, hbv_top_step_D_12, hbv_top_step_E_8, hhv_top_step_Q2_36, hhv_top_step_R2_37);
      VAL   [hhv_fedge_step_D_0=false, hhv_fedge_step_E_1=true, hhv_fedge_step_F_2=true, hhv_fedge_step_G_3=false, hhv_fedge_step_H_4=false, hhv_fedge_step_I_5=false]
[L0]        assume ((!(!hhv_fedge_step_D_0 && !hbv_fedge_step_A_1) && !((!hhv_fedge_step_G_3 || !hbv_fedge_step_C_3) && (hbv_fedge_step_C_3 || hhv_fedge_step_G_3))) && !((!hbv_fedge_step_B_2 || !hhv_fedge_step_F_2) && (hbv_fedge_step_B_2 || hhv_fedge_step_F_2))) && !(hbv_fedge_step_A_1 && hhv_fedge_step_D_0);
      VAL   [hbv_fedge_step_A_1=true, hbv_fedge_step_B_2=true, hbv_fedge_step_C_3=false, hhv_fedge_step_D_0=false, hhv_fedge_step_E_1=true, hhv_fedge_step_F_2=true, hhv_fedge_step_G_3=false, hhv_fedge_step_H_4=false, hhv_fedge_step_I_5=false]
[L0]  CALL  call redge_step(hbv_fedge_step_A_1, hhv_fedge_step_E_1, hbv_fedge_step_B_2, hbv_fedge_step_C_3, hhv_fedge_step_H_4, hhv_fedge_step_I_5);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=true, hhv_redge_step_F_3=false, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=true, hhv_redge_step_D_1=true, hhv_redge_step_E_2=true, hhv_redge_step_F_3=false, hhv_redge_step_G_4=false, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hbv_fedge_step_A_1, hhv_fedge_step_E_1, hbv_fedge_step_B_2, hbv_fedge_step_C_3, hhv_fedge_step_H_4, hhv_fedge_step_I_5);
      VAL   [hbv_fedge_step_A_1=true, hbv_fedge_step_B_2=true, hbv_fedge_step_C_3=false, hhv_fedge_step_D_0=false, hhv_fedge_step_E_1=true, hhv_fedge_step_F_2=true, hhv_fedge_step_G_3=false, hhv_fedge_step_H_4=false, hhv_fedge_step_I_5=false]
[L0]  RET   call fedge_step(hbv_top_step_O_18, hbv_top_step_H_2, hbv_top_step_D_12, hbv_top_step_E_8, hhv_top_step_Q2_36, hhv_top_step_R2_37);
      VAL   [hbv_top_step_A1_15=false, hbv_top_step_A_21=false, hbv_top_step_B1_14=true, hbv_top_step_B_30=false, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=true, hbv_top_step_E1_17=false, hbv_top_step_E_8=false, hbv_top_step_F1_16=true, hbv_top_step_F_7=false, hbv_top_step_G_32=false, hbv_top_step_H_2=true, hbv_top_step_I_3=false, hbv_top_step_K_13=true, hbv_top_step_M_20=true, hbv_top_step_N_26=false, hbv_top_step_O_18=false, hbv_top_step_Q_27=false, hbv_top_step_R_10=false, hbv_top_step_S_9=false, hbv_top_step_T_25=false, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=false, hbv_top_step_X_29=true, hbv_top_step_Y_1=false, hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]  CALL  call fedge_step(hbv_top_step_K_13, hbv_top_step_I_3, hbv_top_step_F_7, hbv_top_step_G_32, hhv_top_step_O2_34, hhv_top_step_P2_35);
      VAL   [hhv_fedge_step_D_0=true, hhv_fedge_step_E_1=false, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=false, hhv_fedge_step_H_4=true, hhv_fedge_step_I_5=false]
[L0]        assume ((!(!hhv_fedge_step_D_0 && !hbv_fedge_step_A_1) && !((!hhv_fedge_step_G_3 || !hbv_fedge_step_C_3) && (hbv_fedge_step_C_3 || hhv_fedge_step_G_3))) && !((!hbv_fedge_step_B_2 || !hhv_fedge_step_F_2) && (hbv_fedge_step_B_2 || hhv_fedge_step_F_2))) && !(hbv_fedge_step_A_1 && hhv_fedge_step_D_0);
      VAL   [hbv_fedge_step_A_1=false, hbv_fedge_step_B_2=false, hbv_fedge_step_C_3=false, hhv_fedge_step_D_0=true, hhv_fedge_step_E_1=false, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=false, hhv_fedge_step_H_4=true, hhv_fedge_step_I_5=false]
[L0]  CALL  call redge_step(hbv_fedge_step_A_1, hhv_fedge_step_E_1, hbv_fedge_step_B_2, hbv_fedge_step_C_3, hhv_fedge_step_H_4, hhv_fedge_step_I_5);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=false, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=false, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hbv_fedge_step_A_1, hhv_fedge_step_E_1, hbv_fedge_step_B_2, hbv_fedge_step_C_3, hhv_fedge_step_H_4, hhv_fedge_step_I_5);
      VAL   [hbv_fedge_step_A_1=false, hbv_fedge_step_B_2=false, hbv_fedge_step_C_3=false, hhv_fedge_step_D_0=true, hhv_fedge_step_E_1=false, hhv_fedge_step_F_2=false, hhv_fedge_step_G_3=false, hhv_fedge_step_H_4=true, hhv_fedge_step_I_5=false]
[L0]  RET   call fedge_step(hbv_top_step_K_13, hbv_top_step_I_3, hbv_top_step_F_7, hbv_top_step_G_32, hhv_top_step_O2_34, hhv_top_step_P2_35);
      VAL   [hbv_top_step_A1_15=false, hbv_top_step_A_21=false, hbv_top_step_B1_14=true, hbv_top_step_B_30=false, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=true, hbv_top_step_E1_17=false, hbv_top_step_E_8=false, hbv_top_step_F1_16=true, hbv_top_step_F_7=false, hbv_top_step_G_32=false, hbv_top_step_H_2=true, hbv_top_step_I_3=false, hbv_top_step_K_13=true, hbv_top_step_M_20=true, hbv_top_step_N_26=false, hbv_top_step_O_18=false, hbv_top_step_Q_27=false, hbv_top_step_R_10=false, hbv_top_step_S_9=false, hbv_top_step_T_25=false, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=false, hbv_top_step_X_29=true, hbv_top_step_Y_1=false, hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]  CALL  call redge_step(hbv_top_step_C_28, hbv_top_step_B1_14, hbv_top_step_M_20, hbv_top_step_N_26, hhv_top_step_L2_31, hhv_top_step_M2_32);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=true, hhv_redge_step_E_2=true, hhv_redge_step_F_3=false, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=true, hhv_redge_step_E_2=true, hhv_redge_step_F_3=false, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hbv_top_step_C_28, hbv_top_step_B1_14, hbv_top_step_M_20, hbv_top_step_N_26, hhv_top_step_L2_31, hhv_top_step_M2_32);
      VAL   [hbv_top_step_A1_15=false, hbv_top_step_A_21=false, hbv_top_step_B1_14=true, hbv_top_step_B_30=false, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=true, hbv_top_step_E1_17=false, hbv_top_step_E_8=false, hbv_top_step_F1_16=true, hbv_top_step_F_7=false, hbv_top_step_G_32=false, hbv_top_step_H_2=true, hbv_top_step_I_3=false, hbv_top_step_K_13=true, hbv_top_step_M_20=true, hbv_top_step_N_26=false, hbv_top_step_O_18=false, hbv_top_step_Q_27=false, hbv_top_step_R_10=false, hbv_top_step_S_9=false, hbv_top_step_T_25=false, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=false, hbv_top_step_X_29=true, hbv_top_step_Y_1=false, hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]  CALL  call redge_step(hbv_top_step_B_30, hbv_top_step_A1_15, hbv_top_step_Q_27, hbv_top_step_R_10, hhv_top_step_J2_29, hhv_top_step_K2_30);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=false, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=false, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hbv_top_step_B_30, hbv_top_step_A1_15, hbv_top_step_Q_27, hbv_top_step_R_10, hhv_top_step_J2_29, hhv_top_step_K2_30);
      VAL   [hbv_top_step_A1_15=false, hbv_top_step_A_21=false, hbv_top_step_B1_14=true, hbv_top_step_B_30=false, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=true, hbv_top_step_E1_17=false, hbv_top_step_E_8=false, hbv_top_step_F1_16=true, hbv_top_step_F_7=false, hbv_top_step_G_32=false, hbv_top_step_H_2=true, hbv_top_step_I_3=false, hbv_top_step_K_13=true, hbv_top_step_M_20=true, hbv_top_step_N_26=false, hbv_top_step_O_18=false, hbv_top_step_Q_27=false, hbv_top_step_R_10=false, hbv_top_step_S_9=false, hbv_top_step_T_25=false, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=false, hbv_top_step_X_29=true, hbv_top_step_Y_1=false, hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]  CALL  call redge_step(hhv_top_step_H1_1, hbv_top_step_E1_17, hbv_top_step_V_19, hbv_top_step_W_31, hhv_top_step_F2_25, hhv_top_step_G2_26);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=false, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]        assume (((((!((!hbv_redge_step_B_1 && (!hhv_redge_step_D_1 || (!hhv_redge_step_C_0 && !hhv_redge_step_E_2))) && ((hhv_redge_step_C_0 || hhv_redge_step_D_1) || hhv_redge_step_E_2)) && !((!hhv_redge_step_F_3 || !hbv_redge_step_A_2) && (hbv_redge_step_A_2 || hhv_redge_step_F_3))) && !hhv_redge_step_H_5) && !(((!hhv_redge_step_D_1 || !hhv_redge_step_C_0) && hbv_redge_step_B_1) && (hhv_redge_step_C_0 || hhv_redge_step_D_1))) && !(hhv_redge_step_C_0 && hhv_redge_step_G_4)) && !((hbv_redge_step_B_1 || hbv_redge_step_A_2) && (!hbv_redge_step_B_1 || !hbv_redge_step_A_2))) && !(!hhv_redge_step_G_4 && !hhv_redge_step_C_0);
      VAL   [hhv_redge_step_C_0=false, hhv_redge_step_D_1=false, hhv_redge_step_E_2=false, hhv_redge_step_F_3=false, hhv_redge_step_G_4=true, hhv_redge_step_H_5=false]
[L0]  RET   call redge_step(hhv_top_step_H1_1, hbv_top_step_E1_17, hbv_top_step_V_19, hbv_top_step_W_31, hhv_top_step_F2_25, hhv_top_step_G2_26);
      VAL   [hbv_top_step_A1_15=false, hbv_top_step_A_21=false, hbv_top_step_B1_14=true, hbv_top_step_B_30=false, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=true, hbv_top_step_E1_17=false, hbv_top_step_E_8=false, hbv_top_step_F1_16=true, hbv_top_step_F_7=false, hbv_top_step_G_32=false, hbv_top_step_H_2=true, hbv_top_step_I_3=false, hbv_top_step_K_13=true, hbv_top_step_M_20=true, hbv_top_step_N_26=false, hbv_top_step_O_18=false, hbv_top_step_Q_27=false, hbv_top_step_R_10=false, hbv_top_step_S_9=false, hbv_top_step_T_25=false, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=false, hbv_top_step_X_29=true, hbv_top_step_Y_1=false, hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]  CALL  call sustain_step(hbv_top_step_A_21, hbv_top_step_C1_4, hbv_top_step_U_5, hbv_top_step_S_9, hbv_top_step_T_25, hhv_top_step_H2_27, hhv_top_step_I2_28);
      VAL   [hhv_sustain_step_C_0=false, hhv_sustain_step_D_1=true, hhv_sustain_step_E_2=false, hhv_sustain_step_F_3=false, hhv_sustain_step_G_4=false, hhv_sustain_step_H_5=false, hhv_sustain_step_I_6=false]
[L0]        assume ((((!((!hhv_sustain_step_G_4 || !hbv_sustain_step_A_2) && (hbv_sustain_step_A_2 || hhv_sustain_step_G_4)) && !((hbv_sustain_step_B_1 && (!hhv_sustain_step_C_0 || !hhv_sustain_step_E_2)) && (hhv_sustain_step_C_0 || hhv_sustain_step_E_2))) && !((!hhv_sustain_step_H_5 || !hhv_sustain_step_E_2) && (hhv_sustain_step_H_5 || hhv_sustain_step_E_2))) && !((hbv_sustain_step_B_1 || hbv_sustain_step_A_2) && (!hbv_sustain_step_B_1 || !hbv_sustain_step_A_2))) && !hhv_sustain_step_I_6) && !(!hbv_sustain_step_B_1 && ((((((hhv_sustain_step_F_3 || hhv_sustain_step_E_2) && !hhv_sustain_step_D_1) && (!hhv_sustain_step_F_3 || !hhv_sustain_step_E_2)) || (hhv_sustain_step_D_1 && hhv_sustain_step_E_2)) && !hhv_sustain_step_C_0) || (hhv_sustain_step_C_0 && !hhv_sustain_step_E_2)));
      VAL   [hhv_sustain_step_C_0=false, hhv_sustain_step_D_1=true, hhv_sustain_step_E_2=false, hhv_sustain_step_F_3=false, hhv_sustain_step_G_4=false, hhv_sustain_step_H_5=false, hhv_sustain_step_I_6=false]
[L0]  RET   call sustain_step(hbv_top_step_A_21, hbv_top_step_C1_4, hbv_top_step_U_5, hbv_top_step_S_9, hbv_top_step_T_25, hhv_top_step_H2_27, hhv_top_step_I2_28);
      VAL   [hbv_top_step_A1_15=false, hbv_top_step_A_21=false, hbv_top_step_B1_14=true, hbv_top_step_B_30=false, hbv_top_step_C1_4=true, hbv_top_step_C_28=false, hbv_top_step_D_12=true, hbv_top_step_E1_17=false, hbv_top_step_E_8=false, hbv_top_step_F1_16=true, hbv_top_step_F_7=false, hbv_top_step_G_32=false, hbv_top_step_H_2=true, hbv_top_step_I_3=false, hbv_top_step_K_13=true, hbv_top_step_M_20=true, hbv_top_step_N_26=false, hbv_top_step_O_18=false, hbv_top_step_Q_27=false, hbv_top_step_R_10=false, hbv_top_step_S_9=false, hbv_top_step_T_25=false, hbv_top_step_U_5=false, hbv_top_step_V_19=false, hbv_top_step_W_31=false, hbv_top_step_X_29=true, hbv_top_step_Y_1=false, hhv_top_step_A2_20=false, hhv_top_step_B2_21=false, hhv_top_step_C2_22=true, hhv_top_step_D2_23=false, hhv_top_step_E2_24=false, hhv_top_step_F2_25=true, hhv_top_step_G1_0=true, hhv_top_step_G2_26=false, hhv_top_step_H1_1=false, hhv_top_step_H2_27=false, hhv_top_step_I1_2=true, hhv_top_step_I2_28=false, hhv_top_step_J1_3=false, hhv_top_step_J2_29=true, hhv_top_step_K1_4=true, hhv_top_step_K2_30=false, hhv_top_step_L1_5=false, hhv_top_step_L2_31=true, hhv_top_step_M1_6=true, hhv_top_step_M2_32=false, hhv_top_step_N1_7=false, hhv_top_step_N2_33=false, hhv_top_step_O1_8=false, hhv_top_step_O2_34=true, hhv_top_step_P1_9=false, hhv_top_step_P2_35=false, hhv_top_step_Q1_10=false, hhv_top_step_Q2_36=false, hhv_top_step_R1_11=false, hhv_top_step_R2_37=false, hhv_top_step_S1_12=false, hhv_top_step_T1_13=false, hhv_top_step_U1_14=true, hhv_top_step_V1_15=false, hhv_top_step_W1_16=false, hhv_top_step_X1_17=false, hhv_top_step_Y1_18=false, hhv_top_step_Z1_19=true]
[L0]  RET   call top_step(hbv_MAIN_V_19, hbv_MAIN_W_20, hbv_MAIN_X_21, hhv_MAIN_C2_17, hbv_MAIN_A_1, hbv_MAIN_B_2, hbv_MAIN_C_3, hbv_MAIN_D_4, hbv_MAIN_E_5, hbv_MAIN_F_6, hbv_MAIN_G_7, hbv_MAIN_H_8, hbv_MAIN_I_9, hbv_MAIN_J_10, hbv_MAIN_K_11, hbv_MAIN_L_12, hbv_MAIN_M_13, hbv_MAIN_N_14, hbv_MAIN_O_15, hbv_MAIN_P_16, hbv_MAIN_Q_17, hhv_MAIN_L1_0, hhv_MAIN_M1_1, hhv_MAIN_N1_2, hhv_MAIN_O1_3, hhv_MAIN_P1_4, hhv_MAIN_Q1_5, hhv_MAIN_R1_6, hhv_MAIN_S1_7, hhv_MAIN_T1_8, hhv_MAIN_U1_9, hhv_MAIN_V1_10, hhv_MAIN_W1_11, hhv_MAIN_X1_12, hhv_MAIN_Y1_13, hhv_MAIN_Z1_14, hhv_MAIN_A2_15, hhv_MAIN_B2_16);
      VAL   [hbv_MAIN_A_1=true, hbv_MAIN_B_2=false, hbv_MAIN_C_3=true, hbv_MAIN_D_4=false, hbv_MAIN_E_5=false, hbv_MAIN_F_6=false, hbv_MAIN_G_7=false, hbv_MAIN_H_8=false, hbv_MAIN_I_9=false, hbv_MAIN_J_10=false, hbv_MAIN_K_11=true, hbv_MAIN_L_12=false, hbv_MAIN_M_13=false, hbv_MAIN_N_14=false, hbv_MAIN_O_15=false, hbv_MAIN_P_16=true, hbv_MAIN_Q_17=false, hbv_MAIN_U_18=true, hbv_MAIN_V_19=true, hbv_MAIN_W_20=false, hbv_MAIN_X_21=true, hhv_MAIN_A2_15=false, hhv_MAIN_B2_16=false, hhv_MAIN_C2_17=false, hhv_MAIN_L1_0=false, hhv_MAIN_M1_1=true, hhv_MAIN_N1_2=false, hhv_MAIN_O1_3=false, hhv_MAIN_P1_4=true, hhv_MAIN_Q1_5=false, hhv_MAIN_R1_6=false, hhv_MAIN_S1_7=false, hhv_MAIN_T1_8=true, hhv_MAIN_U1_9=false, hhv_MAIN_V1_10=true, hhv_MAIN_W1_11=false, hhv_MAIN_X1_12=false, hhv_MAIN_Y1_13=true, hhv_MAIN_Z1_14=false]
[L0]  RET   call MAIN(hbv_ERR_A_2, hbv_ERR_B_3, hbv_ERR_C_4, hbv_ERR_D_5, hbv_ERR_E_6, hbv_ERR_F_7, hbv_ERR_G_8, hbv_ERR_H_9, hbv_ERR_I_10, hbv_ERR_J_11, hbv_ERR_K_12, hbv_ERR_L_13, hbv_ERR_M_14, hbv_ERR_N_15, hbv_ERR_O_16, hbv_ERR_P_17, hbv_ERR_Q_18, hbv_ERR_R_1);
      VAL   [hbv_ERR_A_2=false, hbv_ERR_B_3=true, hbv_ERR_C_4=false, hbv_ERR_D_5=false, hbv_ERR_E_6=true, hbv_ERR_F_7=false, hbv_ERR_G_8=false, hbv_ERR_H_9=false, hbv_ERR_I_10=true, hbv_ERR_J_11=false, hbv_ERR_K_12=true, hbv_ERR_L_13=false, hbv_ERR_M_14=false, hbv_ERR_N_15=true, hbv_ERR_O_16=false, hbv_ERR_P_17=false, hbv_ERR_Q_18=false, hbv_ERR_R_1=false]
[L0]  RET   call ERR();
[L0]  RET   call False();
[L0]        assert false;

  - StatisticsResult: Ultimate Automizer benchmark data
    CFG has 13 procedures, 59 locations, 95 edges, 1 error locations. Started 1 CEGAR loops. OverallTime: 1.9s, OverallIterations: 2, TraceHistogramMax: 12, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 0.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4 SdHoareTripleChecker+Valid, 0.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2 mSDsluCounter, 364 SdHoareTripleChecker+Invalid, 0.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 299 mSDsCounter, 0 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 26 IncrementalHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 0 mSolverCounterUnsat, 65 mSDtfsCounter, 26 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=59occurred in iteration=0, InterpolantAutomatonStates: 7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 1 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 227 NumberOfCodeBlocks, 227 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 91 ConstructedInterpolants, 0 QuantifiedInterpolants, 119 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 97/97 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available
RESULT: Ultimate proved your program to be incorrect!
[2025-04-28 21:21:51,907 INFO  L552       MonitoredProcess]: [MP /usr/bin/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Ended with exit code 0
Received shutdown request...
unsat
